1. Field of the Invention
The present invention relates to a power-up circuit, and more particularly, to an improved power-up circuit which generates a power-up signal using an external supply voltage detection signal and an internal supply voltage detection signal.
2. Description of the Background Art
In recent years, a supply voltage for a memory device has been gradually lowered due to large integration and a minimized semiconductor memory device circuitry. Consequently, an external supply voltage lowered to a predetermined level is employed as an internal supply voltage to operate internal circuits for the memory device.
In order to normally carry out such a semiconductor memory device, the external supply voltage level should be maintained at higher than a predetermined level. Therefore, an initially supplied voltage level is detected during an initial supply voltage input and the power-up signal is then generated to detect that the supply voltage has obtained its predetermined level, thereby controlling significant internal control signals such as /RAS, /CAS.
For that purpose, the conventional semiconductor device detects the level of an external supply voltage externally applied, and when the external supply voltage reaches a predetermined level, the power-up signal is generated. Or the level of the internal supply voltage applied to the internal circuit is detected, and when the internal supply voltage reaches a predetermined level, the power-up signal is generated.
FIGS. 1A and 1B are wave form views illustrating the signal generation in a power-up signal circuit of the conventional semiconductor memory. That is, FIG. 1A is a schematic wave view of the power-up signal generated by detecting the external supply voltage level, and FIG. 1B is a schematic wave view of the power-up signal generated by detecting the internal supply voltage level.
With reference to the drawings, the power-up signal generation process of the conventional semiconductor memory device will now be described.
First, as shown in FIG. 1A, the conventional power-up circuit detects an externally applied supply voltage level Vdd, and generates a "low" level power-up signal PUPB1 at a time point ta when the voltage level becomes a predetermined level Va, and accordingly from that time point, the internal circuit becomes normal in operation.
When the external voltage Vdd is supplied, it is lowered down to a predetermined level so that it takes a predetermined time to generate an internal voltage Vint required for the internal circuit. Therefore, the time interval (Ta.about.Tint) ranging from the time point ta when the power-up signal PUPB1 is generated, to a time point when the internal voltage Vint is generated remains at a state in which a normal level supply voltage is not applied to the internal circuit, so that at this time an unstable operation may occur during an access from the external device. Further, an excessive current such as latch-up may occur due to the instability in internal nodes.
FIG. 1B is a view illustrating a power-up circuit of the conventional semiconductor memory device to solve the above problem. As shown therein, the internal supply voltage level Vint is detected and the "high" level power-up signal PUPB2 is generated for a predetermined time period at a time point tb when the voltage becomes a predetermined level Vb and accordingly the respective states of the memory devices are reset as an initializing process. Then, there begins a normal operation of the internal circuit.
However, in such a power-up circuit, although it is possible to reset the input at an unstable state in which a normal level internal supply voltage Vint is generated by the power-up signal PUPB2, since the power-up signal PUPB2 maintains a "low" level at intervals 0.about.tb which are prior to the generation of the power-up signal PUPB2, the subsequent unstable state still exists, thereby disadvantageously generating an excessive current such as a latch-up.